module RegIdEx (
    RegDst_in, 
    Branch_in, 
    MemtoReg_in, 
    AluOp_in, 
    MemWrite_in, 
    AluSrc_in, 
    RegWrite_in, 
    Jump_in, 
    Sign_in,
    DataType_in,
    DataSign_in,
    pc_in,
    data_rs_in,
    data_rt_in,
    immediate_in,
    instr1_in,
    instr2_in,
    instr,
    clk,
    RegDst_out, 
    Branch_out, 
    MemtoReg_out, 
    AluOp_out, 
    MemWrite_out, 
    AluSrc_out, 
    RegWrite_out, 
    Jump_out, 
    Sign_out,
    pc_out,
    data_rs_out,
    data_rt_out,
    immediate_out,
    instr1_out,
    instr2_out,
    instr_out,
    DataType_out,
    DataSign_out

);
    input [1:0]  RegDst_in;      
    input [1:0]  Branch_in;      
    input [1:0]  MemtoReg_in;    
    input        AluSrc_in;      
    input [3:0]  AluOp_in;  
    input        MemWrite_in;    
    input        RegWrite_in;    
    input [1:0]  Jump_in;        
    input        Sign_in;
    input [1:0]  DataType_in;
    input        DataSign_in;
    input [31:0] pc_in;
    input [31:0] data_rs_in;
    input [31:0] data_rt_in;
    input [15:0] immediate_in;
    input [4:0]  instr1_in;
    input [4:0]  instr2_in;
    input [31:0] instr;
    input clk;


    output reg [1:0]   RegDst_out;      
    output reg [1:0]   Branch_out;      
    output reg [1:0]   MemtoReg_out;    
    output reg         AluSrc_out;      
    output reg [3:0]   AluOp_out;  
    output reg         MemWrite_out;    
    output reg         RegWrite_out;    
    output reg [1:0]   Jump_out;        
    output reg         Sign_out;
    output reg [1:0]   DataType_out;
    output reg         DataSign_out;
    output reg [31:0]  pc_out;
    output reg [31:0]  data_rs_out;
    output reg [31:0]  data_rt_out;
    output reg [15:0]  immediate_out;
    output reg [4:0]   instr1_out;
    output reg [4:0]   instr2_out;
    output reg [31:0]  instr_out; 
    
    always @(posedge clk) begin
        RegDst_out  <= RegDst_in;
        Branch_out   <= Branch_in;
        MemtoReg_out  <= MemtoReg_in;
        AluSrc_out  <= AluSrc_in;
        AluOp_out <= AluOp_in;
        MemWrite_out <= MemWrite_in;
        RegWrite_out <= RegWrite_in;
        Jump_out <= Jump_in;
        Sign_out <= Sign_in;
        DataType_out <= DataType_in;
        DataSign_out <= DataSign_in;
        pc_out <= pc_in;
        data_rs_out <= data_rs_in;
        data_rt_out <= data_rt_in;
        immediate_out <= immediate_in;
        instr1_out <= instr1_in;
        instr2_out <= instr2_in;
        instr_out <= instr;
        
    end

endmodule //reg_id_ex